This article assumes you have a NEEK (NIOS embedded evaluation kit) and that you have installed
Quartus II 9.1 sp1 and NIOS IDE. I am writing this article while experimenting, so be warned: there
may be inaccuracies, wrong definitions, bad phrasing, etc. But I hope experienced users will
drop me a line to correct my mistakes.
1. Scope of this article
As I started learning FPGA technology a few days ago, I wanted to do at once a video demonstration
using a complete FPGA project downloaded from Altera's site. It failed, I don't know why, so I decided
to go back to the basics, build a simple system from scratch, and don't go forwards (at least not too
far) unless I know what I am doing. After all, as a piano hobbyist, I'm aware that it is difficult to play
Beethoven without some background training. So it must be the same for FPGAs.
So, lets write the specs:
- I want to build a full working system from an empty project;
- I want this system to blink leds.
I hope this is not too ambitious…
So what we have to do is a hardware part and a software part. The hardware part will consist in
defining a processor (NIOS) to be implemented in the FPGA, and the software part will consist
in programming this processor for flashing leds. In this article, I will concentrate on the FPGA
hardware development only. The easy part (software) will be described in another article.
NB: the images of this tutorial are shown in 320 width format. All the images that are more
thatn 320 wide can be enlarged. Just click the images.
2. Definition of the hardware
This part consists in 3 steps:
1. Creating an empty project
2. Adding elements (NIOS, memory, etc) to this project
3. Tuning verilog files
2.1 Creating an empty project
You have to setup a development folder.Careful: there should be no spaces in names and paths.
I have setup a folder directly on C:\ and named it "FPGA". The first test will be in a folder called FPGATest. You can
create it now or create it using "new folder" when Quartus II asks you for the path.
Go to Windows' start menu and choose:
programs -> altera -> Quartus II 9.1 sp1 Web Edition -> Quartus II 9.1 sp1 Web Edition
The Quartus development environment starts up and lets you choose what to do. If you just installed,
there shouldn't be any existing recent project. Anyway, choose "create new project".
Click image to enlarge.
At this point, there is an information window. You may click "don't show me this introduction again".
Click next.
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2.1.1 Setting project path (screen 1/5)
A window shows up, prompting you for project name and path. As explained earlier, I have created
a folder called "FPGA" just on the root. "FPGA" will be the location of my FPGA projects. Now I will
create another folder called FPGATest using the navigation window from Quartus. If you didn't change
anything, the default path should be c:\altera\91sp1\quartus. Use the "…" to browse to the new location.
Go to C:\FPGA, click the new folder icon, and add an arbitrary name. For instance FPGATest
The project name is arbitrary, I have chosen "MyFirstFPGA", just to show some originality. I am also
asked for the top level design entity.
As it was filled automatically, I left it as is. Click next.
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2.1.2 Including files (screen 2/5)
As this is a new, empty project, there is nothing to do here (at least I hope). Click next.
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2.1.3 Setting device (screen 3/5)
Assuming you start from scratch, there will be a default device set. In my case, "stratix III".
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Change this to the proper device (Cyclone III in case of the above-mentioned NEEK). Then
filter the available devices at the right. First enter "FBGA". Then change the number of pins
to 324 and change the speed grade to 6. Only 2 devices will remain. Choose the first one (EP3C25..).
Then click next.
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2.1.4 Setting external tools (screen 4/5)
As a guess, I will not use any external tool, so I think I can skip this one.
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2.1.5 Summary (screen 5/5)
This is just a confirmation window, and there is no reason to get anything wrong. Click finish.
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There will be a short commercial message from ALTERA, informing you about the advantages
of the license version, and then you will be brought to the Quartus development environment
window. Here is the topleft part of this window:
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At this point, one could think that the empty project is fully created since the paths are set
and the device kind has be chosen. However, for some reason, it is sometimes necessary to
come back to the settings. Click the settings icon (a little pencil in the toolbar, at the right
of the project title, MyFirstFPGA in this tutorial).
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In the case the device is different to what it should be, you have to set the device parameters
similarly as in 2.1.3.
Now that's it, the project is created.
3. Adding elements to the FPGA
Now we are going to build the system itself on the FPGA. As said in paragraph 1, nothing
fancy for the time being. Only blinking LEDs with the NIOS processor.
What we have to do is basically:
- Create a processor on the FPGA;
- Add memory to this processor (the NIOS has no default memory);
- Add an input / output port to flash leds;
- Add a JTAG interface to communicate with the PC.
For this, we are going to use the SOPC builder. The SOPC builder can be started by going
to the "Tools" menu and selecting "SOPC builder". This latter menu is preceded with a small
icon that you can also find in the toolbar, just before the help icon. Once you start the SOPC
builder, you will have the following popup, prompting you for a project name.
Enter any name, for example "niostest". Leave the verilog option as is and click OK.
Now you should obtain a window as follows. At that point, you may rename the clock
as you wish, for instance to "sysclock"
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3.1 Adding a processor
The system is currently empty. We are going to first add a NIOS processor.
The SOPC builde has a library of objects on the left (that we will simply call "library"
from now on). Expand the "processors" item (click the little "+" preceeding the
"processors" list item). There is a single processor, the NIOS II. Double-click it, or
select it and click "ADD...". A window pops up to choose a variant of the processor.
Here is the top-left part of this window.
Click image to enlarge.
In this first hardware, we are going to use the simplest processor, the NIOS II/e.
Click finish for the time being. There are info messages labeled "to do" and one warning.
We will come back later to set memory parameters, but there is no memory yet. The window
should look like this. As there is only one CPU, you may rename it to "cpu" (right-click on
cpu_0 and choose "rename".
Click image to enlarge.
3.2 Adding memory
Now we are going to add some memory. Go back to the library tree (in the left
part of the above window) and expand "memories and memory controllers. There
are a few memory types and also subclasses.
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Expand "On chip" and choose the last item, On-chip memory (RAM or ROM). Double-click
or select and click "Add…". A memory setup window pops up.
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The default was 4096 bytes. Set it to 32768. There are some warnings. This can be solved
easily by following the warning message (it says that the base address should be set to
0x00008000) or simply by selecting System->Auto-assign base addresses.
Now you may rename the memory to something shorter, for instance onchip_mem.
Note that there are "to do" information items. When we added the CPU at paragraph 3.1,
we said that we would come back to the CPU setting, so it is the right time now.
Double-click cpu.
Click image to enlarge.
Change the settings of both Reset Vector and Exception Vector. The pulldown menu has
only one option, so there will be no hesitation at this point. Note that even before
clicking finish, the main window's "to do" warnings have disappeared. Click finish.
3.3 Add an IO port
Select Peripherals > Microcontroller Peripherals > PIO (Parallel I/O) and click Add.
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A popup window will open for port setup.
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Specify 4 for the port width (default is 8), and specify output ports only.
Click finish. Now we have one processor, some memory and LED outputs.
You may choose to rename the PIO. For instance led_pio. The last thing
we are going to add is a JTAG interface in order to load a program to the NIOS
processor.
3.4 Add a JTAG interface
Select Interface Protocols > Serial > JTAG UART and click Add.
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The following window pops up. Leave it as it is and click finish.
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You may rename the JTAG interface as "jtag". Now your SOPC builder window should look
like this:
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Press Generate. It will ask you if you want to save your file (in my case niostest.sopc). Press
yes and fech a cup of coffee, it will take a few minutes depending on the machine
you use. You should get no errors. Once the system generation is finished you can click exit
to go back to the Quartus development environment.
Click image to enlarge.
4. Verilog top file, pin assignment
At this point, the internals of the FPGA are built. But we still have to tell the system
to which pin the external hardware is connected to.
If you choose File->open (or click the proper icon), you will notice that a certain number of
files have been generated.
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4.1 Make the top verilog file
Open the file "niostest_inst.v".
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This file gives you an example of instantiation for the system, and it can be used just
by adjusting the naming.
Create a file for your top level object (defined in 2.1.1. "MyFirstFPGA.v" in this tutorial).
You can create this file with file menu->new->Verilog HDL file and save it as "MyFirstFPGA.v".
(the system should setup the name "MyFirstFPGA" automatically).
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4.2 Pin assignment
Now the FPGA internals are fully defined, but we still need to assign the pins (i.e. tell the system
to what external pin should the clock, reset and LEDs be connected.
For this, there is a pin assignment tool called Pin Planner. In order to find pin names easily,
you may open another QUARTUS II window of an ALTERA source project and copy the pin names.
Another method to get half of the job for free: compile your project. It should compile, but
you will get critical warnings like this: No exact pin location assignment(s) for 6 pins of 6 total
pins (in the current configuration, 4 leds + clock + reset). But when you subsequently open the
pin planner, the name of your top level file signals will be already in the file. Copy the locations
from an existing file. This should look like this:
Click image to enlarge.
Set the physical location of each pin: by double-clicking the location column, you get a drop
down menu from which you can select the proper pin name. Another solution is to select the
cell you want to fill and fill it with the keyboard. Once all the pins are entered, close the
pin planner.
4.3 Compilation
Press the purple right arrow in the menu bar. The compilation ends with no errors, but with
quite a few warnings. This seems to be normal. In my case, there remain a few critical
warnings which do not prevent the system to work:
"Critical warning: the following clock transfres have no clock uncertainty assignment. For more
acurate results, apply clock uncertainty assignments or use the dreive_clock_uncertainty command".
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4.4. Loading your design
The last step of this tutorial consists in loading your design to the FPGA.
Go to Tools->Programmer. The following window should pop up.
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This should be the default settings. Adapt if necessary. Press start, and the program
(in my case "MyFirstFPGA.sof") should load.
I loaded the program, and the 4 leds LED1 ~ LED4 are on.
Now I will end the design here and try to compile a program on the NIOSII.
This will be the subect of the 3rd part of this tutorial.
For those who would be interested in having a look at the current status, here is an archive of the project.
Pascal