This will be the second experiment.
This post is currently under writing, so don't expect a working tutorial
for the time being. It will be improved in the coming days / week, depending on how
much time I can spend on it.
In the first experiment, I have built a system from scratch on a Cyclon III FPGA using
Altera's NEEK. As the internal memory is very small (32k), it does not allow a lot to be
perform on the processor. So the next step is to get some room for program execution.
In this topic, I will add a SSRAM to the NIOS processor.
1. Building the system into the FPGA
This part will be basically the same as this one until the end of point 3 (just before
generating).
1.1. First steps
If you have made the first tutorial, copy the projet to another folder.
If not, go back to the first tutorial and do it until point 3.
I have restarted another project from scratch, which will be good for practice.
It is stored in C:\FPGASSRAMTest in my case, and the top-level entity is called NIOS_SRAM.
The system name has been set to ssramtest. Therefore the names should be changed accordingly.
Differences with the first tutorial:
- As we are going to set 1 MB of SSRAM, we don't need 32k of internal RAM anymore. I am not sure
we need it at all, but when looking at other projects, there is always a certain amount of internal
RAM, maybe used as a cache. I have restarted the project from scratch, and set the amount of
internal RAM to 4k.
- The SSRAM we are going to add will be used for programming. Therefore, the CPU setting
(at the end of point 3.2 in the first tutorial) will have to be changed after setting SSRAM.
1.2 Adding SSRAM
Once you have the NIOS processor configured with internal RAM, PIO and JTAG, then you can
add the SSRAM. Choose Memories and memory controllers -> SRAM -> Cypress Cy7C1380C.
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The following a window pops up.
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The NEEK memory's capacity is 1 MBytes, so change the default (2) to 1. Click finish.
You may want to rename the memory to SSRAM.
At this point, you will notice an error message saying that SSRAM must be connected to
an Avallon-MM tristate master.
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No hesitation, just do what is requested. Go to Bridges and adapters, and choose
memory mapped -> Avallon MM tristate bridge. The following window pops up.
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Leave it as is and click finish. You may rename the bridge and the SSRAM.
At this point you may notice that there are a lot of errors.
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The reason is just a base address assignment. The devices address overlap, so a reassignment
is needed. It can be done by manually reassigning the address, but the simplest way to do it
is to go to the system meny and choose "auto-assign base addresses".
At this point, ther shouldn't be any error anymore. If you have restarted a new project from
scratch, there are still "to do" messages.
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Remember that in the first tutorial, we had to set the CPU "reset vector" and "exception
vector" to the base address of the internal memory. Now we use SSRAM, so we are going to
set the proper parameters. Double-click cpu.
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In the reset vector and exception vector fields, choose "ssram" (or another label depending
on how you have renamed the ssram). Click finish.
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Now the SOPC builder work is basically finished.
2. Verilog top file, pin assignment
Generate your design. It takes a few minutes (depending on your computer). This should end
without error or warnings.
2.1 Verilog top file
We have to create the verilog top file (NIOS_SRAM.v).
Open the file with the name ending with "_inst.v".
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This is an instantiation example that you can use almost is, as shown in the following
code snippet.
- Code: Select all
// Define the module inputs and outputs
module NIOS_SSRAM (
CLOCK,
RESET,
LED_PIO,
SRAM_ADD,
SRAM_DAT,
SRAM_OE_N,
SRAM_CE_N,
SRAM_ADSC_N,
SRAM_BW_N,
SRAM_BWE_N
);
input CLOCK;
input RESET;
output [3:0] LED_PIO;
output [23:0] SRAM_ADD;
inout [31:0] SRAM_DAT;
output SRAM_OE_N;
output SRAM_CE_N;
output SRAM_ADSC_N;
output [3:0] SRAM_BW_N;
output SRAM_BWE_N;
// Instantiate the NIOSII processor
ssramtest ssramtest_inst (
.address_to_the_ssram (SRAM_ADD),
.adsc_n_to_the_ssram (SRAM_ADSC_N),
.bw_n_to_the_ssram (SRAM_BW_N),
.bwe_n_to_the_ssram (SRAM_BWE_N),
.chipenable1_n_to_the_ssram (SRAM_CE_N),
.data_to_and_from_the_ssram (SRAM_DAT),
.out_port_from_the_led_pio (LED_PIO),
.outputenable_n_to_the_ssram (SRAM_OE_N),
.reset_n (RESET),
.sysclk (CLOCK)
);
endmodule
2.2 Pin assignment
The following pins have to be assigned to the physycal pins of the FPGA (Item / numbre of pins):
CLOCK, 1
RESET, 1
LED_PIO, 4
SRAM_ADD, 24
SRAM_DAT, 32
SRAM_OE_N, 1
SRAM_CE_N, 1
SRAM_ADSC_N, 1
SRAM_BW_N, 4
SRAM_BWE_N 1
Total : 70 pins.
For the pin assignment, you can use pin planner. Enter the signal name at <new node>
and then the location. Don't worry about the direction, it will be set automatically at compile
time. If you don't want to look on schematics one by one where those pins are conneced to,
you can open an existing sample project and open its pin assignment. For example, I have
opened NEEK_VIP_demo_LCD_SVGA_v91_2. Double click the file cycloneIII_3c25_niosII_video
and open the pin planner. The pin assignment looks like this:
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Note that in the video example, the pins of the ssram are called top_flash_ssram_a.
The reason of "flash_ssram" is that the flash and the ssram of the board share the same bus.
The suffix _a means address. Similarily, the suffix _d means data.
As the video example is quite complicated, there are many pins that we can disregard.
Therefore, it is possible to filter what is shown. If you want to focus on the addresses,
you can enter "*ssram_a*" in the "Named:" field. The "*" are wildcards.
You may wonder why there is no top_flash_ssram_a[0] but only _a[1] to _a[25]. This is
because there are 2 types of memory. The flash is in 16-bit format and the ssram in 32
bit format. Setting the data until A1 addresses 2 bytes (flash output format), so the bit
a[0] is not necessary.
Enter the 70 pins as in the video example and you're done. Compile the whole system
(purple right arrow in Quartus II window).
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As you can see, there are some errors. Open Assign -> Device. The following window
pops up.
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Click the "Device and pin options" button. The following window pops up.
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Change the pin options as follows.
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Close the two windows (OK) and recompile.
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To do:
I am trying to connect the SSRAM clock right now. It can still not work for the time
being. I am trying to clear this issue. That should be done in the coming days depending
on my other projects. Stay tuned!
Pascal